During the manufacturing process, integrated circuits (ICs) must be quickly tested to determine whether each integrated circuit is functioning correctly without any physical defects. One common approach is scan testing, which allows an initial state to be loaded into an integrated circuit and tests to be performed from that initial state.
A specific state can be loaded into an integrated circuit by designing into the integrated circuit a special mode called a “scan mode” where all the state elements in the integrated circuit are chained together into one or more shift registers called scan chains. The integrated circuit can then be placed on automatic test equipment (ATE), which initializes the integrated circuit to a state (e.g., scan pattern) through the scan chains, applies some tests on the integrated circuit from the state, and then uses the scan chains to unload response data from the integrated circuit after the tests have been applied.
To determine whether an integrated circuit is functioning correctly, unloaded response data from an integrated circuit is compared against a known good response. If the responses do not match, the integrated circuit is identified as faulty. This process is repeated for different scan patterns until the integrated circuit can be validated as functioning defect free.
There are several aspects of scan testing that make it practical. First, it is possible to apply a large number of tests to an integrated circuit in a short amount of time. Second, hardware overhead required to incorporate a scan mode into the integrated circuit is typically not significant compared to functional logic of the integrated circuit. Finally, it is possible to diagnose response data to determine which part of the integrated circuit is failing.
Today's designs with geometries smaller than 130 nanometers (nm) may include millions of state elements. Such large designs are now stressing the limits of the scan testing approach because of excessive test data volume, increasing test application time, and escalating test costs. To reduce test storage requirements and decrease test application time, scan-based test compression techniques have become common. To decrease hardware overhead, these test compression techniques tend to reduce the accuracy of the results. This makes the diagnosis of failures and yield problems more difficult.
Scan compression techniques can also impact the design methodology for large integrated circuits. Designers of large integrated circuits often use a hierarchical approach. The overall design of an integrated circuit is broken down into smaller parts. Different design teams are responsible for completing their assigned parts of the integrated circuit. The design activities of the different parts occur in parallel with very little synchronization. One part of the design may be completed long before another part, or in some cases, parts may be acquired from a third party design vendor.
A major limitation of existing test compression solutions for integrated circuits is that existing test compression solutions require that the compression logic be added after the design's parts have been integrated. In addition, the entire integrated circuit is required to be tested all together and all at the same time. As a result, it is very difficult to apply existing test compression solutions to an integrated circuit that is hierarchical designed because of the constraints placed on the design of the integrated circuit by the test logic. These constraints can add additional steps to the design methodology very late in the design cycle, which increases schedule risk.